MAX5878EGK+D【PDF 9/19 页】IC DAC 16BIT DUAL 250MSPS 68-QFN

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MAX5878

16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

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Dynamic Performance Parameter Definitions

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital sam-

ples, the theoretical maximum SNR is the ratio of the full-

scale analog output (RMS value) to the RMS quantization

error (residual error). The ideal, theoretical minimum can

be derived from the DAC’s resolution (N bits):

SNRdB = 6.02dB x N + 1.76dB

However, noise sources such as thermal noise, reference

noise, clock jitter, etc., affect the ideal reading; therefore,

SNR is computed by taking the ratio of the RMS signal to

the RMS noise, which includes all spectral components

minus the fundamental, the first four harmonics, and the

DC offset.

Noise Spectral Density

The DAC output noise floor is the sum of the quantiza-

tion noise and the output amplifier noise (thermal and

shot noise). Noise spectral density is the noise power in

1Hz bandwidth, specified in dBFS/Hz.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the carrier fre-

quency (maximum signal components) to the RMS

value of their next-largest distortion component. SFDR

is usually measured in dBc and with respect to the car-

rier frequency amplitude or in dBFS with respect to the

DAC’s full-scale range. Depending on its test condition,

SFDR is observed within a predefined window or to

Nyquist.

Two-/Four-Tone Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc (or dBFS)

of the worst 3rd-order (or higher) IMD product(s) to either

output tone.

Adjacent Channel Leakage Power Ratio (ACLR)

Commonly used in combination with wideband code-

division multiple-access (W-CDMA), ACLR reflects the

leakage power ratio in dB between the measured

power within a channel relative to its adjacent channel.

ACLR provides a quantifiable method of determining

out-of-band spectral energy and its influence on an

adjacent channel when a bandwidth-limited RF signal

passes through a nonlinear device.

Settling Time

The settling time is the amount of time required from the

start of a transition until the DAC output settles its new

output value to within the converter’s specified accuracy.

Glitch Impulse

A glitch is generated when a DAC switches between

two codes. The largest glitch is usually generated

around the midscale transition, when the input pattern

transitions from 011...111 to 100...000. The glitch

impulse is found by integrating the voltage of the glitch

at the midscale transition over time. The glitch impulse

is usually specified in pVs.

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